1. Field of the Invention
The present invention relates to a pattern processing apparatus for processing circuit patterns such as ICs or VLSICs formed on a semiconductor wafer, photographic mask or reticle and more particularly to a laser processing apparatus for projecting a spot of laser beam on a portion of a circuit pattern to cut the lead or anneal the selected area.
2. Description of the Prior Art
With the recent remarkable advance in increasing the circuit density and fineness of semiconductor devices, mass production techniques have been rapidly developed for the fabrication of semiconductor memories (e.g., RAMs and ROMs) each having a memory capacity of 1 megabits, 4 megabit or as large as 16 megabits, within a chip which is several millimeters square. Generally, semiconductor devices are formed on a circular semiconductor wafer by means of a lithographic process. With conventional conductor devices not so high in circuit density, e.g., semiconductor memories and the like, it has been the usual practice that after semiconductor devices (hereinafter referred to as chips) have been formed on a wafer, the chips are cut off or separated from each other by a wafer scriber and are placed in appropriate packages. In the case of memories having greater capacities and devices whose line width is the circuitry is reduced to 1 .mu.m, however, there has been an increasing need for inspecting the chips formed on a wafer by the use of a wafer prober and a tester as to whether the individual chips properly function electrically. By so inspecting, it is possible to prevent deterioration of the productivity due to the chips being judged as reject chips after their packaging.
Then, manufacturing techniques of the presently available higher-density chips include one which is referred to as a redundancy process. This process performs the processing in the following manner. For instance, while essentially a semiconductor memory is only required to have a given number of memory cells, e.g., 1 megabits, or 4 megabit, spare cells or redundant cells (redundant circuits) are preliminarily prepared within the same chip during the manufacture in consideration of the possibility that only a part of the cells becomes defective. Then, if any defective portions are detected as a result of the inspection by the wafer prober, the spare cells are interconnected in place of the reject cells and the reject chip is saved.
This interconnection of the spare cells in the redundancy process is performed by projecting a condensed spot (several .mu.m) of laser beam and cutting the special leads (which are generally called fuses and often made of a material such as polysilicone) or projecting the spot to the high-resistance interconnect layers and converting them to low-resistance interconnect layers. This type of apparatus employing a laser beam for the processing of articles is known as a so-called laser processing apparatus and it has also been used in the past as a laser trimming for adjusting the resistance value of resistors with a high degree of accuracy. Then, where the interconnection lines within any chip on a wafer are to be processed, it is essential to accurately project a laser beam to the interconnection line at any position on the wafer and a high degree of accuracy of about 0.3 .mu.m is for example required. Therefore, a laser processing apparatus designed to perform the redundancy process is usually provided with an alignment optical system for aligning the laser spot with such high accuracy.
With this type of laser processing apparatus, however, its component parts suffer aging during a long period of use, thus causing a so-called drifting phenomena in which there occurs a difference between the working position detected by the alignment optical system and the actual working position by the laser beam projected through the projection lens as will be described hereunder.
In other words, the relative positional relation between the projection lens and the alignment optical system is essentially constant and not changing and the detection of a working center is effected on this premise. However, this relative positional relation is subject to variation due to the aging of the component parts as mentioned previously. Thus, there is a disadvantage that even if the processing is effected by arranging the projection lens opposite to the working center detected by the alignment optical system, the working center of the laser beam fails to coincide with the desired working center and the working position is shifted.
A similar disadvantage is caused when the chip itself on the wafer is deformed by the lithographic operation. Such deformation that can be caused by the lithographic operation is generally referred to as lithographic deformation and it often is a distortion peculiar to the exposure apparatus used in the exposure operation of the chips.
The presently available exposure apparatus are mainly divided into three types, i.e., optical type, X-ray type and electron (valence electron) type and the optical-type exposure apparatus are classified into a batch exposure type, slit scan type and projection type. In the case of these optical-type exposure apparatus, when the light image of a circuit pattern on a mask or reticle is projected onto a wafer, there exists more or less an optical distortion, e.g., a distortion of the image due to the aberration of the projection optical system or a run-out error due to an error in the projection magnification. On the other hand, the X-ray exposure apparatus are mainly of the proximity type and thus there is the danger of causing a deformation resulting in a small difference in size between the printed pattern and the pattern on the mask depending on the setting accuracy of a gap between the mask and the wafer.
Also, in the case of the electron-beam exposure apparatus, there is the danger of deforming a printed pattern with respect to a design pattern due to, for example, the aberration of the electron lens for deflecting the electron beam.
Such a lithographic distortion may also be caused by factors other than the exposure apparatus, i.e., the various treatments performed in the course of the wafer processing. During the wafer processing, the wafer is sometimes heated and this causes the occurrence of a run-out in the wafer on the whole. The occurrence of a run-out in the wafer results in a delicate deviation of the chip array on the wafer from the design values. This deviation is more manifest in the chips near the marginal portion of the wafer and the amount of deviation of the chip$ increases with increase in the size or the diameter of the wafer. The deviations of the chips due to the occurrence of a run-out in the wafer is considered to consist of their offsets in the x and y directions with respect to the design chip array and they can hardly take the form of deformations tending to change the form of the chips themselves. In any events, there is a disadvantage that since the chips on the wafer involve such lithographic deformations as those caused by the exposure apparatus and the processing operations, a processing reject is caused if the amount of such lithographic deformation approaches the spot size of the laser processing apparatus.
Also, one method of preventing any error due to such lithographic deformation is to preliminarily measure the accurate position of each fuse by projecting the attenuated processing laser beam on each fuse and detecting the resulting diffracted light or the scattered light. However, this method gives rise to another disadvantage of considerably deteriorating the throughput due to the need to measure the position of each fuse. Moreover, in this method the processing laser beam, though attenuated, is projected on some portions of the circuits in the chip and thus there is the danger of causing serious damages to the circuit pattern of the CMOS structure, for example.